The 224-gigabit problem inside every AI rack
The AI buildout has one of these problems right now. It is not GPUs. It is not power. It is not water. It is the humble, unglamorous business of moving bits between chips.
Here is the shape of it. An Nvidia GB200 NVL72 rack contains 72 Blackwell GPUs stitched together with roughly 5,000 copper cables and something like two miles of wiring. Inside that rack, GPU-to-GPU traffic runs at 1.8 terabytes per second per link. To hit those numbers, the individual electrical lanes have to push 224 gigabits per second, up from 112 the generation before, up from 56 the generation before that. Every doubling is a fresh war with physics. Copper attenuates. Optical burns power. Both need signal conditioning that gets exponentially harder each time the frequency climbs.
Most investors think about AI infrastructure in three boxes: the chip (Nvidia, AMD, Broadcom), the memory (SK Hynix, Micron, Sandisk), and the power (Vertiv, Eaton, the utilities). They mostly ignore the fourth box, which is the interconnect, because it sounds like plumbing. It is not plumbing. It is the reason a 72-GPU rack can behave like one giant computer instead of 72 arguing ones. Get the interconnect wrong and your $3 million rack throttles down to the speed of its slowest link. Get it right and you sell to every hyperscaler on earth for the next decade.
The companies that solve this problem have a peculiar profile. They are not household names. They rarely appear on CNBC. They sell into a handful of customers (Microsoft, Meta, Amazon, Google, Oracle, plus the neoclouds) and their entire business rides on being designed into the next generation of rack architecture 18 months before anyone at retail hears the product name. Miss a design win and you are out for a cycle. Win one and you compound at 40% for years.
What makes this cycle different is the shift from copper to optical inside the rack. Copper works fine at short distances and lower speeds. Once you cross 224 gigabits per lane and start scaling out beyond a single rack into multi-rack pods (which is what Rubin and MI400 architectures require in 2026 and 2027), copper physically cannot carry the signal without unacceptable power draw. So the industry is moving to a mix of active electrical cables for the short hops and co-packaged optics for everything longer. Both need specialised signal integrity silicon (retimers, DSPs, PHYs) that only three or four companies in the world can design at the current node.
That is the entire game. Three or four companies. Every AI rack shipped between now and 2028. A total addressable market that JPMorgan pegged at $8 billion this year and something like $30 billion by 2029.
One of those three or four companies is on the banned list this week. Another is roughly a $10 billion market cap that most Alexandria readers already know about. A third trades at a valuation that assumes everything goes right forever. And then there is a fourth. Smaller. Older. Founded in 2008 by two ex-Marvell engineers who spent a decade grinding on SerDes IP nobody wanted, until 2023, when hyperscalers realised they needed exactly what these two had been building the whole time.
They have a product line called HiWire. They have a partnership with every hyperscaler you can name and several you cannot. Their last quarter grew revenue 179% year over year. They are guiding to another sequential acceleration this quarter as the Rubin transition begins in earnest.
And they are still under $20 billion in market cap.
Three or four companies in the world can design 224-gigabit signal integrity silicon at the current node. One of them still trades under $20 billion.
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