Micron just printed $25 billion in one quarter. Here's what that number actually means.
The cycle is still real. What's changed is that Micron has partially opted out of it.
The mechanism is something called strategic customer agreements, sixteen of them, covering roughly 20% of DRAM volume and 30% of NAND. These aren't handshake deals. There's $100 billion in contractual floor-price revenue locked across multiple years and $22 billion in cash deposits already sitting on Micron's balance sheet, placed by customers to secure supply. The floor prices written into those contracts are set above any gross margin Micron has ever printed in a prior upcycle.
The headline numbers, 84.9% gross margin, $25.11 EPS, $41.5 billion in revenue up 346% year over year, are extraordinary on their own. But the gross margin figure is almost a distraction from the more important structural point: Micron has gotten its largest customers to prepay for memory and agree to minimum prices through 2030. When the next downcycle comes, and eventually one will, Micron's floor won't be where it was in 2019 or 2022.
Now trace one link further. Mehrotra was specific about supply constraints: greenfield fab lead times stretching years, EUV complexity compressing the number of qualified manufacturers, HBM trade ratios that consume vastly more wafer area per gigabyte shipped, and skilled-trades shortages at the Idaho and New York build-outs. These aren't Micron-specific problems. Samsung and SK Hynix face identical constraints. Which means the pricing power Micron is locking into its SCAs through 2030 isn't a company-specific bet. It's an industry condition that all three of the serious HBM suppliers are now operating inside.
For ASML (NASDAQ:ASML) and the equipment supply chain feeding Micron's expansion, this call is a demand confirmation with a timeline attached. Micron's Singapore packaging facility comes online for HBM volume in H1 2027. That's a hard date, and equipment orders flow years in advance of it. The Idaho and New York fabs add more runway beyond that.
The second-order consequence most people are missing: every hyperscaler that signed an SCA handed Micron something more valuable than revenue. They handed Micron a window into their own AI infrastructure roadmaps. The 16 customers whose names Micron won't disclose had to show Micron their demand curves out to 2030 to justify the deposit structure. Micron now has better visibility into AI compute growth than most analysts covering the sector.
At 91 on our confidence index, this was the most certain earnings call we've tracked in the current cycle. Mehrotra's pitch went up on the $25 billion line in a way that didn't sound staged. The man running one of the most capital-intensive businesses on the planet sounded like he'd finally built something that doesn't need to apologize to the cycle.
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Credo Technology Group Holding Ltd
As hyperscalers push toward 800G and 1.6T Ethernet and the interconnect distances inside clusters shrink, the performance and power efficiency of the physical link layer matters enormously. Credo is selling directly into that constraint. Its customers are hyperscalers and large OEMs, the same names signing Micron's strategic customer agreements.
At a score of 92 on our internal ranking, this is a company worth spending a weekend on before the broader market figures out that the AI infrastructure trade isn't just about compute. The connectivity layer is where a lot of the next round of spending lands, and Credo is already inside it.
The AI infrastructure trade isn't peaking. It's entering its most capital-intensive phase yet.
Hyperscalers didn't just order memory. They placed $22 billion in cash deposits and signed floor-price contracts through 2030. You don't do that if you think utilization is about to catch up with capacity. You do that when your internal demand models are showing you something alarming about how much memory next-generation model training and inference actually requires.
The HBM trade ratio is the number most people aren't tracking: each HBM chip consumes substantially more wafer area than conventional DRAM. As models scale and inference volumes compound, the memory requirement per AI job grows faster than compute. The buildout isn't slowing. The mix is shifting toward the most supply-constrained, highest-margin products in the memory industry. That's not a cycle topping out. That's a cycle changing its character.