Micron just printed the most important earnings call in semiconductor history
The headline numbers were extraordinary: 84.9% gross margin, $25.11 earnings per share, $41.5 billion in revenue up 346% year-over-year. But the number that actually matters came buried in the prepared remarks: $100 billion in contractual floor-price revenue locked across sixteen strategic customer agreements, with $22 billion in cash deposits already sitting on Micron's (NASDAQ:MU) balance sheet from customers who haven't taken delivery yet.
Think about what that means structurally. Micron's customers, the hyperscalers and AI infrastructure builders, are paying Micron in advance. They are depositing cash to reserve future HBM capacity because they cannot risk being caught short. The floor prices on those contracts are set above any gross margin Micron has ever printed in a prior upcycle. This is not a cyclical memory company anymore. The business model has changed.
Mehrotra has been telegraphing this shift for two years, and the skeptics, including me at points, looked at the history of DRAM cycles and said: it always comes back down. Oversupply arrives, ASPs collapse, margins crater. That is how memory has worked since the 1980s.
Here is why this cycle may be different, and I want to be precise about the word "may" because the history is real. HBM is not standard DRAM. The conversion ratio from standard DRAM wafers to HBM is roughly 3:1, meaning each HBM unit consumes three times the wafer capacity of equivalent standard memory. Every AI accelerator Nvidia ships requires HBM stacks. Every new GPU generation requires more HBM than the last. So as AI accelerator volumes climb, HBM demand climbs faster than anyone initially modeled, while simultaneously consuming supply that would otherwise address the standard DRAM market.
On top of that, Mehrotra named the supply constraints explicitly: greenfield fab lead times measured in years, EUV tool scarcity, HBM packaging complexity, and skilled-trades shortages at the new Idaho and New York fabs. These are not Micron-specific problems. Samsung and SK Hynix face the same constraints. The tightness Micron is pricing into contracts through 2030 reflects industry capacity, not one company's production schedule.
For ASML (NASDAQ:ASML), for advanced packaging players, and for every equipment supplier on Micron's build-out, this call was a demand confirmation worth more than any analyst note. Micron just told the market it is pulling in clean room capacity, that its Singapore packaging facility contributes to HBM volume from the first half of 2027, and that customers are willing to pay deposits years in advance to secure allocation.
The bear case is real and worth stating clearly: if AI capex hits a wall, if hyperscaler spending stalls, if a recession forces IT budget cuts, those SCA floor prices get tested and the deposit structure faces legal scrutiny rather than smooth execution. AI infrastructure spending has never been tested in a genuine downturn.
But if the bear case doesn't materialize in the next 18 months, Micron is sitting on a contractual revenue base that makes it look less like a cyclical memory supplier and more like a toll road on AI compute. That re-rating hasn't fully happened yet.
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The SCA structure at Micron makes the old memory cycle thesis obsolete
But the SCA structure changes the math in a way that cycle analysis doesn't capture. Customers depositing $22 billion in cash in advance are not doing that for a commodity they can source elsewhere. They are paying for guaranteed HBM allocation they cannot get from Samsung or SK Hynix fast enough to meet their GPU production schedules. The deposit is an admission of dependency.
The bear case requires believing either that AI accelerator demand collapses before 2030, or that Samsung and SK Hynix ramp HBM capacity fast enough to break the pricing floor despite identical fab lead times and EUV constraints. Both are possible. Neither looks probable on an 18-month horizon. The cycle thesis isn't wrong forever. It just may be wrong long enough to matter.